RelMicroS IPs empower customers with the cutting edge solution they need to deliver reliable microelectronic systems characterized with high-efficiency, high-performance, and low-power designs for the leading-edge nodes.
RelMicroS IP Portfolio
3. Clocking IP
RelMicroS Clocking IP is a set of cutting-edge IP designs that includes phase-locked loops (PLLs), and delay-locked loops (DLLs) to address the requirements of microelectronic systems where capture range and clock performance are crucial.
2.1. Phase-locked loops (PLLS) and delay-locked loops (DLLs)
- Low jitter.
- Wide input and output frequency ranges.
- Fast lock.
- Compact size.
- Low power dissipation.
- Wide operating temperature range: -40°C to 125°C.
Design for Reliability
Intensive scaling for VLSI circuits is a key factor for gaining outstanding performance. However, this scaling has huge negative impact on the circuit reliability. As it increases the undesired effect of degradation and decreases the robustness of ultradeep submicrometer technologies operating in harsh environments.
RelMicroS is challenging this negative impact of scaling process, as RelMicroS uses state-of-the-art design techniques to provide fault tolerance designs, believing that creativity, efficiency, and performance are worthless if they are not served with an equal amount of reliability.
- GDSII layout (.gds).
- Timing model (.lib).
- Verilog HDL behavioral model (.v).
- Footprint abstract (.lef).
- Netlist (.cdl).
- Physical verification reports: DRC / LVS / ERC / ESD / ANT.
- Datasheet with integration guidelines (.pdf).